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? semiconductor components industries, llc, 2002 january, 2002 rev. 7 1 publication order number: mc10198/d mc10198 monostable multivibrator the mc10198 is a retriggerable monostable multivibrator. two enable inputs permit triggering on any combination of positive or negative edges as shown in the accompanying table. the trigger input is buffered by schmitt triggers making it insensitive to input rise and fall times. the pulse width is controlled by an external capacitor and resistor. the resistor sets a current which is the linear discharge rate of the capacitor. also, the pulse width can be controlled by an external current source or voltage (see applications information). for highspeed response with minimum delay, a hispeed input is also provided. this input bypasses the internal schmitt triggers and the output responds within 2 nanoseconds typically. output logic and threshold levels are standard mecl 10,000. test conditions are per table 2. each apreconditiono referred to in table 2 is per the sequence of table 1. ? p d = 415 mw typ/pkg (no load) ? t pd = 4.0 ns typ trigger input to q ? 2.0 ns typ hispeed input to q ? min timing pulse width pw qmin 10 ns typ 1 ? max timing pulse width pw qmax >10 ms typ 2 ? min trigger pulse width pw t 2.0 ns typ ? min hispeed pw hs 3.0 ns typ trigger pulse width ? enable setup time t set 1.0 ns typ ? enable hold time t hold 1.0 ns typ ? 1 c ext = 0 (pin 4 open), r ext = 0 (pin 6 to v ee ) ? 2 c ext = 10 mf, r ext = 2.7 kw http://onsemi.com device package shipping ordering information mc10198l cdip16 25 units / rail mc10198p pdip16 25 units / rail mc10198fn plcc20 46 units / rail marking diagrams 1 16 a = assembly location wl = wafer lot yy = year ww = work week cdip16 l suffix case 620 mc10198l awlyyww pdip16 p suffix case 648 plcc20 fn suffix case 775 10198 awlyyww 1 1 16 mc10198p awlyyww
mc10198 http://onsemi.com 2 dip pin assignment v cc1 q q c ext e pos r ext ext.pulse width control v ee v cc2 high-speed input n/c trigger input n/c n/c e neg n/c 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 pin assignment is for dualinline package. for plcc pin assignment, see the pin conversion tables on page 18 of the on semiconductor mecl data book (dl122/d). logic diagram v cc1 = pin 1 v cc2 = pin 16 v ee = pin 8 5 7 10 13 15 3 2 q q 64 v ee v cc c ext e pos external pulse width control e neg trigger input hi-speed input truth table e pos e neg l l h h input output l h l h triggers on both positive & negative input slopes triggers on positive input slope triggers on negative input slope trigger is disabled r ext 1. at t = 0 a.) apply v ihmax to pin 5 and 10. b.) apply v ilmin to pin 15. c.) ground pin 4. 2. at t 10 ns a.) open pin 1. b.) apply 3.0 vdc to pin 4. hold these conditions for 10 ns. 3. return pin 4 to ground and perform test as indicated in table 2. pins 1, 16 = v cc = ground pins 6, 8 = v ee = 5.2 vdc outputs loaded 50 w to 2.0 vdc v ih max v il min p1 -5.0 0 10 ns t(ns) -4.0 -3.0 -2.0 -1.0 0(gnd) 10 20 pin 1 open 30 table 1 e precondition sequence pin 4 voltage (vdc) 10 ns table 2 e conditions for testing output levels (see table 1 for precondition sequence) v ila max v il min p2 v iha max v il min p3
mc10198 http://onsemi.com 3 pin conditions pin conditions test p.u.t. 5 10 13 15 test p.u.t. 5 10 13 15 precondition precondition v oh 2 v il min v oha 2 v iha min p1 v oh 3 p1 v oha 3 v ila max p1 precondition precondition v ol 3 v il min v ola 3 v ila max v ol 2 p1 v ola 2 v iha min precondition precondition v oha 2 v ila max v ola 2 v il min v oha 3 v iha min v ola 3 v il min precondition precondition v oha 2 v il min v ola 3 p2 v oha 3 p3 v ola 2 p3 precondition precondition v oha 2 p2 v ola 3 v ih max p2 v oha 3 p3 v ola 2 v ih max p3 precondition precondition v oha 2 v ih max p2 v ola 3v iha min v ih max p1 v oha 3 v ih max p3 v ola 2v ila max v ih max p1 precondition precondition v oha 2 v ih max p1 v ola 3v ih max v iha min p1 v oha 3 v ih max p1 v ola 2v ih max v ila max p1
mc10198 http://onsemi.com 4 electrical characteristics test limits pin under 30 c +25 c +85 c characteristic symbol u n d er test min max min typ max min max unit power supply drain current i e 8 110 80 100 110 madc input current i inh 5, 10 13 15 415 350 560 260 220 350 260 220 350 m adc i inl 5 0.5 0.5 0.3 m adc output voltage logic 1 v oh 2 3 1.060 1.060 0.890 0.890 0.960 0.960 0.810 0.810 0.890 0.890 0.700 0.700 vdc output voltage logic 0 v ol 2 3 1.890 1.890 1.675 1.675 1.850 1.850 1.650 1.650 1.825 1.825 1.615 1.615 vdc threshold voltage logic 1 v oha 2 3 1.080 1.080 0.980 0.980 0.910 0.910 vdc threshold voltage logic 0 v ola 2 3 1.655 1.655 1.630 1.630 1.595 1.595 vdc switching times (50 w load) trigger input t t+q+ t tq+ 3 3 2.5 2.5 6.5 6.5 2.5 2.5 4.0 4.0 5.5 5.5 2.5 2.5 6.5 6.5 ns high speed trigger input t hs+q+ 3 1.5 3.2 1.5 2.0 2.8 1.5 3.2 ns minimum timing pulse width pw qmin 3 10.0 ns maximum timing pulse width pw qmax 3 >10 ms min trigger pulse width pw t 3 2.0 ns min hispd trig pulse width pw hs 3 3.0 ns rise time (20 to 80%) 3 1.5 4.0 1.5 3.5 1.5 4.0 ns fall time (20 to 80%) 3 1.5 4.0 1.5 3.5 1.5 4.0 ns enable setup time t setup (e) 3 1.0 ns enable hold time t hold (e) 3 1.0 ns 1. the monostable is in the timing mode at the time of this test. 2. c ext = 0 (pin 4 open); r ext = 0 (pin 6 tied to v ee ). 3. c ext = 10 m f (pin); r ext = 2.7k (pin 6). 4. v ihmax v ilmin p1
mc10198 http://onsemi.com 5 electrical characteristics (continued) test voltage values (volts) @ test temperature v ihmax v ilmin v ihamin v ilamax v ee 30 c 0.890 1.890 1.205 1.500 5.2 +25 c 0.810 1.850 1.105 1.475 5.2 +85 c 0.700 1.825 1.035 1.440 5.2 pin under test voltage applied to pins listed below (v ) characteristic symbol under test v ihmax v ilmin v ihamin v ilamax v ee (v cc ) gnd power supply drain current i e 8 6, 8 1, 4, 16 input current i inh 5, 10 13 15 5,10 13 15 6, 8 6, 8 6, 8 1, 4, 16 1, 4, 16 1, 4, 16 i inl 5 5 6, 8 1, 4, 16 output voltage logic 1 v oh 2 3 13 ( 4. ) 13 6, 8 6, 8 1, 4, 16 1, 4, 16 output voltage logic 0 v ol 2 3 13 ( 4. ) 13 6, 8 6, 8 1, 4, 16 1, 4, 16 threshold voltage logic 1 v oha 2 3 15 15 6, 8 6, 8 1, 16, 4 1, 16, 4 threshold voltage logic 0 v ola 2 3 15 15 6, 8 6, 8 1, 16, 4 1, 16, 4 switching times (50 w load) +1.11v pulse in pulse out 3.2 v +2.0 v trigger input t t+q+ t tq+ 3 3 10 5 13 13 3 3 6, 8 6, 8 1, 16, 4 1, 16, 4 high speed trigger input t hs+q+ 3 15 3 6, 8 1, 16, 4 minimum timing pulse width pw qmin 3 note 2. 6, 8 1, 16, 4 maximum timing pulse width pw qmax 3 note 3. 6, 8 1, 16, 4 minimum trigger pulse width pw t 3 13 3 6, 8 1, 16, 4 minimum hispd trigger pulse width pw hs 3 15 3 6, 8 1, 16, 4 rise time (20 to 80%) 3 6, 8 1, 16, 4 fall time (20 to 80%) 3 6, 8 1, 16, 4 enable setup time t setup (e) 3 5 3 6, 8 1, 16, 4 enable hold time t hold (e) 3 5 3 6, 8 1, 16, 4 1. the monostable is in the timing mode at the time of this test. 2. c ext = 0 (pin 4 open); r ext = 0 (pin 6 tied to v ee ). 3. c ext = 10 m f (pin); r ext = 2.7k (pin 6). 4. v ihmax v ilmin p1 each mecl 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibr ium has been established. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is ma intained. outputs are terminated through a 50ohm resistor to 2.0 volts. test procedures are shown for only one gate. the other gates are tested in the same manner.
mc10198 http://onsemi.com 6 switching time test circuit and waveforms @ 25 c 50ohm termination to ground located in each scope channel input. all input and output cables to the scope are equal lengths of 50ohm coaxial cable. wire length should be < 1/4 inch from tp in to input pin and tp out to output pin. unused outputs are tied to a 50ohm resistor to ground. high-speed trigger input tp out external pulse width control e pos 5 0.1 m f v cc1 = v cc2 = +2.0 vdc 0.1 m f coax v in tp in input pulse generator r ext c ext hi-speed input trigger input 6 e neg 4 7 10 13 15 coax 25 m f v ee = -3.2 vdc v out 2 q q 3 0.1 m f +1.11 v input pulse t+ = t- = 2.0 0.2 ns (20 to 80%) t hs+q+ q pw hs pw q 50% 50% pw t q trigger input t t+q+ e pos 50% 50% t t-q+ pw q t setup (e) t hold(e)
mc10198 http://onsemi.com 7 applications information circuit operation: 1. pulse width timing e the pulse width is determined by the external resistor and capacitor. the mc10198 also has an internal resistor (nominally 284 ohms) that can be used in series with r ext . pin 7, the external pulse width control, is a constant voltage node (3.60 v nominally). a resistance connected in series from this node to v ee sets a constant timing current i t . this current determines the discharge rate of the capacitor: where d t = pulse width d v = 1.9 v change in capacitor voltage then: if r ext + r int are in series to v ee : i t = [(3.60 v) (5.2 v)] [r ext + 284 w ] i t = 1.6 v/(r ext + 284) the timing equation becomes: d t = [(c ext )(1.9 v)] [1.6 v/(r ext + 284)] d t = c ext (r ext + 284) 1.19 where d t = sec r ext = ohms c ext = farads figure 2 shows typical curves for pulse width versus c ext and r ext (total resistance includes r int ). any low leakage ca- pacitor can be used and r ext can vary from 0 to 16 kohms. 2. triggering ethe e pos and e neg inputs control the trigger input. the mc10198 can be programmed to trigger on the positive edge, negative edge, or both. also, the trigger input can be totally disabled. the truth table is shown on the first page of the data sheet. the device is totally retriggerable. however, as duty cycle approaches 100%, pulse width jitter can occur due to the re- covery time of the circuit. recovery time is basically depen- dent on capacitance c ext . figure 3 shows typical recovery time versus capacitance at i t = 5 ma. i t = c ext d v d t d t = c ext 1.9 v i t v ee = -5.2 v -3.60 v external pulse width control 284 w r int mc10198 r ext figure 1 e c ext 6 4 7 10 k w r ext = 0 3 k w 500 w c ext - timing capacitance 10 pf 10 figure 2 timing pulse width versus c ext and r ext 100 10 1 0.1 m f 100 1000 pf 100 pf 0.01 m f note: total resistance = r ext + r int pulse width (s) c ext - timing capacitance 0.01 m f 100 pf 1000 pf 100 ns 0.1 m f 10 m s 1 m s 1 ns 10 ns 10 pf figure 3 e recovery time versus c ext @ i t = 5 ma recovery time m
mc10198 http://onsemi.com 8 3. hispeed input e this input is used for stretching very narrow pulses with minimum delay between the output pulse and the trigger pulse. the trigger input should be disabled when using the highspeed input. the mc10198 triggers on the rising edge, using this input, and input pulse width should narrow, typically less than 10 nanoseconds. usage rules: 1. capacitor lead lengths should be kept very short to minimize ringing due to fast recovery rise times. 2. the e inputs should not be tied to ground to establish a high logic level. a resistor divider or diode can be used to establish a 0.7 to 0.9 voltage level. 3. for optimum temperature stability; 0.5 ma is the best timing current i t . the device is designed to have a constant voltage at the external pulse width control over temperature at this current value. 4. pulse width modulation can be attained with the external pulse width control. the timing current can be altered to vary the pulse width. two schemes are: a. the internal resistor is not used. a dependent cur- rent source is used to set the timing current as shown in figure 4. a graph of pulse width versus timing current (c ext = 13 pf) is shown in figure 5. b. a control voltage can also be used to vary the pulse width using an additional resistor (figure 6). the current (i t + i c ) is set by the voltage drop across r int + r ext . the control current ic modifies i t and alters the pulse width. current i c should never force i t to zero. r c typically 1 k w . figure 5 e pulse width versus i t @ c ext = 13 pf 0.01 ma 0.1 ma 1 ma 10 ma 1000 100 10 pulse width (ns) mc10198 figure 4 e c ext 7 4 i figure 6 e -5.2 v control voltage 284 r ext c ext 6 4 7 i t + i c i t i c -3.6 v r c i t - timing current
mc10198 http://onsemi.com 9 5. the mc10198 can be made nonretriggerable. the q output is fed back to disable the trigger input dur- ing the triggered state (logic diagram). figure 7 shows a positive triggered configuration; a similar configuration can be made for negative triggering. figure 7 e -0.9 v q q 64 v ee v cc e pos external pulse width control e neg trigger input hi-speed input r ext c ext
mc10198 http://onsemi.com 10 package dimensions plcc20 fn suffix plastic plcc package case 77502 issue c notes: 1. datums -l-, -m-, and -n- determined where top of lead shoulder exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum -t-, seating plane. 3. dimensions r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). m n l y brk w v d d s l-m m 0.007 (0.180) n s t s l-m m 0.007 (0.180) n s t s l-m s 0.010 (0.250) n s t x g1 b u z view dd 20 1 s l-m m 0.007 (0.180) n s t s l-m m 0.007 (0.180) n s t s l-m s 0.010 (0.250) n s t c g view s e j r z a 0.004 (0.100) t seating plane s l-m m 0.007 (0.180) n s t s l-m m 0.007 (0.180) n s t h view s k k1 f g1 dim min max min max millimeters inches a 0.385 0.395 9.78 10.03 b 0.385 0.395 9.78 10.03 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 --- 0.51 --- k 0.025 --- 0.64 --- r 0.350 0.356 8.89 9.04 u 0.350 0.356 8.89 9.04 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y --- 0.020 --- 0.50 z 2 10 2 10 g1 0.310 0.330 7.88 8.38 k1 0.040 --- 1.02 ---
mc10198 http://onsemi.com 11 package dimensions cdip16 l suffix ceramic dip package case 62010 issue t notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension f may narrow to 0.76 (0.030) where the lead enters the ceramic body. a b t f e g n k c seating plane 16 pl d s a m 0.25 (0.010) t 16 pl j s b m 0.25 (0.010) t m l dim min max min max millimeters inches a 0.750 0.785 19.05 19.93 b 0.240 0.295 6.10 7.49 c --- 0.200 --- 5.08 d 0.015 0.020 0.39 0.50 e 0.050 bsc 1.27 bsc f 0.055 0.065 1.40 1.65 g 0.100 bsc 2.54 bsc h 0.008 0.015 0.21 0.38 k 0.125 0.170 3.18 4.31 l 0.300 bsc 7.62 bsc m 0 15 0 15 n 0.020 0.040 0.51 1.01 16 9 18 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 pdip16 p suffix plastic dip package case 64808 issue r
mc10198 http://onsemi.com 12 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc10198/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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